RS TDC fixes, Installation of L1.1 trigger

                                                
                                                          R. Tschirhart
                                                          P. Cooper    
                       Summary of RS-TDC work, 6/5-6/6/01. 

1)  Generic RS-485 cable plant problems:  On arrival, an inspection of
    the cable plant revealed that the strain-relief backing on the    
    34-pin RS-485 cables that chain between DYC outputs was not installed
    on several connectors.  The main role of the strain-relief backing is
    to provide a surface for the DYC connector latch-eject fingers to    
    contact so that a tight fit is assured.  At least two of these   
    connectors (DYC5 & DYC6) were found to be cocked out of tight 
    position.  Strain-relief backing was added to these connectors,
    and they were plugged back in again tightly.                   

2)  Module #33 Bad Header Problem:  We started first with this problem,
    which we could not reproduce.  This could possibly have been a result
    of the poorly seated DYC RS-485 cables, which were fixed before this 
    problem was studied.  Peter developed a CAMAC CFSA tool that can be 
    used to issue single CAMAC instructions.  We were able to read/write
    the VSN bytes of the TDC headers through CAMAC without trouble.     

3)  We used the test pusler delay/fanout modules to test TDCs, one module
    at a time.  We explicitly loaded Delay=0 into the delay/fanout modules
    with F16(A0->F) data=0.  This module doesn't support readback.  Using 
    the fanout we found and fixed the following problems:                
                                                         
      a)  Generic problem with DYC5:  After lots of investigation we
          found that pin#1 on the RS-485 34-pin output connector on
          the DYC had been bent out of contact.  The pin was so badly
          bent we decided to install a spare DYC.  On replacing the
          DYC the problems associated with this DYC readout block were
          fixed.

4)  Modules #12 and #30 remain out of the readout.  Some work was done
    on Module #30 to recover it.  TDC module was swapped after noting 
    that a FERA control bus pin that must be clipped off to allow for
    connector bulk wasn't cut cleanly and pushed the connector off the
    pins a bit.  On replacing the TDC and cabling it back into the DYC
    chain, the readout would still hangup.                            

5)  Implemnted and tested the MPI cable plant to all 6 DYCs.  Four
    new FERA control harnesses replaced four of the control harnesses
    that did not have a breakout pair of conductors for the MPI signal.
    Two-pin ECL twisted pairs were run from each control bus MPI
    breakouts to a NIM->ECL converter NIM module.  The corresponding
    six NIM inputs were supplied by a neighboring NIM FAN-in/FAN-out
    module that fanned out the single MPI signal.  Unfortunately the
    L1.1 trigger system wasn't working, so we cobbled up an MPI
    fast-clear-gate and fast-clear signal that was triggered off of
    the received common stop signal.  With George Redlinger we studied
    the front-end behaviour when the fast clear leading edge fell inside
    and outside the fast-clear-gate.  All six DYCs readout correctly
    when the leading edge of the fast clear was outside the gate, and
    all DYCs did not readout (as expected) when the fast clear leading
    edge fell within the fast-clear-gate.  Signals required to drive
    the MPI system:

      a)  A single NIM Fast Clear signal from the trigger that plugs
          into the NIM Fast CLear fan-in/fan-out.  Labeled.

      b)  A single NIM Fast-Clear-Gate from the trigger that plugs
          into the NIM Fast-Clear-Gate fan-in/fan-out.  Labeled.  This
          trailing edge of this gate must extend for at least 100 nsec
          after the the latest possible Fast Clear leading edge time.

Remaining Problems and Issues:

A)  Modules #12 ad #30 still can't be readout.  TDCs and FERA control
    harnesses were swapped without fixing  the problem.  This may be
    the result of a race condition in the DYC readout that we don't
    understand:  Readout works with 6 TDCs in four of our crates and
    only 5 TDCs in two of our crates.  Could be that we are on some
    kind of timing edge.

B)  L1.1 MPI abort logic needs to be tested with real the real L1.1
    system.

C)  We do not have a spare DC2.  Next trip from Fermilab should bring
    one.  We should also get our DAWN VME crate and Indy returned back
    to Fermilab.